Technology – Research and Innovation

Selected Technical Publications (2011)

  1. Sensitivity of LWR and CD linearity to process conditions in active area (Proceedings Paper)
    Guy Ayal, Elena Malkes, Efraim Aharoni, Shimon Levi, Amit Siany, Ofer Adan, Eitan Shauly and Yosi Shacham-Diamand, SPIE 7971, 79711Q (2011); doi:10.1117/12.879322.
  2. Standard cell electrical and physical variability analysis based on automatic physical measurement for design-for-manufacturing purposes (Proceedings Paper)
    Eitan Shauly, Allon Parag, Hafez Khmaisy, Uri Krispil, Ofer Adan, Shimon Levi, Sergey Latinski, Ishai Schwarzband and Israel Rotstein, SPIE 7974, 797410 (2011); doi:10.1117/12.881841.
  3. Process Integration aspects of back illuminated CMOS Imagers using Smart Stacking Technology with best in class direct bonding
    R. Shima Edelstein; O.Katz, B.Lavi, I. Aberman., S. Rosenthal., M. Shadmi., S,Arad., Nili Golan, M. Shach Caplan, and M. Massalha. C. Lagahe-Blanchard., L.Marinier, R. Fontanière., A. Castex., M. Broekaart., M.Martinez., N.Milhet., A.Rigny2, C. Pelissier. 2011 International Image Sensor Workshop (IEEE), June 8-11, 2011, Hokkaido, Japan. Pages 240-243.
  4. Nonvolatile low-voltage memory transistor based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals
    V. Mikhelashvili, B. Meyler, S. Yofis,Y. Shneider, A. Zeidler, M. Garbrecht, T. Cohen-Hyams, W. D. Kaplan, M. Lisiansky, Y. Roizin, J. Salzman and G. Eisenstein, Appl.Pys.Lett. 98, 212902, 2011.
  5. The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2–HfO2 stacks and Au nanocrystals
    V. Mikhelashvili, B. Meyler, M Garbrecht, S. Yofis, J. Salzman, T. Cohen-Hyams, W.Kaplan, Y. Roizin, M. Lisiansky, and G. Eisenstein, Microelectronic Engineering, No2. 2011 964–968.